ASIC RTL Design Manager, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
• 15 years of experience in ASIC RTL design.
• Experience with RTL design using Verilog/System Verilog and microarchitecture.
• Experience with ARM-based SoCs, interconnects and ASIC methodology.

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Engineering.
• Experience driving multi-generational roadmap for IP development.
• Experience leading interconnect IP design team for low power SoCs.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Responsibilities

• Lead a team of people to deliver fabric interconnect design.
• Develop and refine RTL design to aim power, performance, area, and timing goals.
• Define details such as interface protocol, block diagram, data flow, pipelines, etc.
• Oversee RTL development, debug functional/performance simulations.
• Communicate and work with multi-disciplined and multi-site teams.