Design Verification Engineer, Security

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
• 3 years of experience in verifying IP or digital systems that include components like CPU, Direct Memory Access, interconnects, Memory Management Unit, peripherals and memories.
• Experience creating and using verification components and environments in a standard verification methodology such as Universal Verification Methodology.
• Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification.

Preferred qualifications:

• Experience in verification of security block, Hardware Security Modules, crypto blocks.
• Experience with Fault injection based verification of Automotive or Security blocks.
• Experience with Perl or Python scripting, including developing or enhancing Design Verification (DV) flows.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Plan the verification of complex Security hardware IPs at IP and subsystem level by understanding the design specification and interacting with Architecture and Design Engineers to identify important verification scenarios.
• Create and enhance verification environments using System Verilog and Universal Verification Methodology (UVM). Identify and write all types of coverage measures for stimulus.
• Debug tests with design engineers to deliver design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.
• Collaborate with Software, Silicon Validation, and Silicon bring up teams.