IBM LOGIC DESIGN ENGINEER – Cache

• Lead the Architecture Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems.
• Design and architect L2 cache and LLC as driven by capacity latency bandwidth and RAS requirements.
• Develop the features present the proposed architecture in the High level design discussions
• Develop micro-architecture Design RTL Collaborate with Verification DFT Physical design FW SW teams to develop the feature
• Signoff the Pre-silicon Design that meets all the functional area and timing goals
• Participate in silicon bring-up and validation of the hardware
• Lead a team of engineers guide and mentor team members represent as Logic Design Lead in global forums.
• Estimate the overall effort to develop the feature.
• Estimate silicon area and wire usage for the feature.
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