Intern-Design Engineering

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Digital Verification Intern

WARSAW OFFICE / HYBRID

FULL TIME or PART TIME

If you would like to gain first experience in SoC design/verification - join our team for an internship! As Intern DV Engineer you will have an opportunity to co-create complete virtual components from design specification through the verification process up to providing a complex SoC design. Develop yourself by working with professionals!

The candidate should have:

• BSc in Electronic / Micro-Electronic Engineering or Computer Science - or equivalent/last year student
• Basic knowledge of digital electronics and Hardware Description Languages (HDL)
• Basic understanding of OOP
• Good English skills

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• Experience in digital design
• Knowledge of verification methodology OVM/UVM, SVA, Formal
• Knowledge of Python, Tcl/Tk, other scripting

• Flexible working hours which will allow you to combine education with gaining practical experience
• Opportunity to complete your BSc or MSc project/thesis with Cadence
• Competitive salary package adequate to competencies; based on internship / civil agreements that could be converted to regular contract of employment based on performance;
• Work under the guidance of experienced team managers and designers,
• Continuous professional development; trainings and seminars;
• Possibility to cooperate with people from around the world in an expanding global organization;
• Multisport cards;
• Social Fund benefits;
• And much more, so do not hesitate to contact us.