Layout Design Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in VLSI, Computer Engineering, or equivalent practical experience.
• 5 years of experience designing and drawing layout of high-speed/low power memories.
• 5 years of experience with layout verification activities like DRC, LVS, Latch-Up, or EMIR and Density Checks.
• Experience with developing memory array layout (e.g., row decoders, write drivers, assist circuits, sense amplifiers, memory control circuit) in 3nm (or equivalent) technology nodes.

Preferred qualifications:

• Master's degree in VLSI, Computer Engineering, or a related field.
• Experience drawing layout for sense amplifiers, decoders, assist circuits, latches, flip-flops, isolation cells, power switches, and level shifters.
• Experience with placement, track planning and integration of various blocks within SRAM memories.
• Experience with Virtuoso XL and Extraction tools such as Star-RC/QFS.
• Understanding of layout design rules, layout dependent effects and DFM in FinFET technology nodes.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Analyze design specifications from Compute IP's and develop custom memory arrays or standard-cells.
• Draw schematics, extract layout, write spice deck and run spice simulations to validate the circuit (or block).
• Run high-speed sigma analysis to understand sensitivity of designed circuit.
• Work with layout engineers to improve the Performance, Power, Area (PPA) of memory arrays or standard-cells.
• Collaborate with Physical Design team and ensure seamless integration of standard-cells or memory arrays.