Senior Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Successful applicant will participate in the design and development of a fully configurable and fully featured Network on Chip (NoC) product.

Responsibilities include hardware architecture and micro-architecture definition, as well as RTL design to achieve high performance and low power.

Familiarity with NoC technology and concepts, AMBA protocols (AXI, AHB, APB) as well as coherency protocols (ACE, CHI) required.

Company Information:

Cadence is the global leader in software, hardware, and services that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.

Cadence is an equal opportunity employer and is committed to hiring a diverse workforce.

The annual salary range for California is $192,500 to $357,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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