Signal and Power Integrity Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 5 years of industry experience in the SI/PI field.
  
• Experience in industry SIPI modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc).

Preferred qualifications:

• Experience in collaborating with cross-functional teams, including chip top design, physical design, Static Timing Analysis (STA), package, and system teams.
  
• Experience with 2.5D/3D package design (e.g., silicon interposer, silicon bridge, 3D die stacking, STA, Voltage budget).
• Expertise in signal and power integrity for various high speed interconnects (e.g., HBMx, D2D, Ethernet, PCIe and etc).

Familiarity with post Si test environment on memory or high speed serdes.

Familiarity to next generation memory and chiplet standards and timing budget methodology.

Excellent programming and data analysis skill with Matlab, Python, C++ and etc to establish automation flows and data processing.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will lead chip and package design, ensuring optimal Signal Integrity/Power Integrity (SI/PI) performance and system co-design from concept to production. Collaborating within a cross-functional team, including Chip Design, IP, System Design, software, and vendors, you will drive signal and power design implementations on chip and advanced packages.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Drive chip-package-system co-design by performing SI/PI analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc for High Performance Computing based on 2.5D/3D package technology.
• Conduct post Si validation and qualification of high speed interface for New Product Introduction (NPI). Development of next generation memory interface considering Input/Output Physical Layer (IO PHY), SI/PI and physical design.
• Provide feedback on chip floorplan considering package/system routability and SI/PI. High speed Interface IP evaluation.
• Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design goal, define boundaries of chip design and explore SI/PI and Design for Manufacturingtradeoff for package design closure for production.
• Develop Methodologies to enhance accuracy and productivity, and external vendor management.