Silicon Design Verification Engineer

Minimum qualifications:

• Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
• 3 years experience verifying digital logic at RTL level using SystemVerilog for FPGAs or ASICs.
• Experience verifying digital IP and subsystems.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.
• Experience creating/using verification components and environments in Universal Verification Methodology (UVM), Verification Methodology Manual (VMM), Open Verification Methodology (OVM).
• Experience with image processing, computer vision, or machine learning applications.
• Experience in prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.

Experience with performance verification of ASIC components.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Vefication Methodology (UVM) or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.