System Performance Modelling

Introduction
As a Hardware Developer at IBM you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today’s market.

Your Role and Responsibilities
As a HW performance Analyst you will lead the hardware bringup Pre-silicon & post-silicon performance validation Performance monitoring unit validation and work closely with hardware development team to ensure model performance and the hardware performance correlates. You are also responsible to ensure server class systems IBM develops meet its performance objective and targets. You will also be responsible for leading modelling effort of key sub-systems like cache interconnect memory controller etc. As a performance lead you will also be working on exploring & implementing innovative ways to improve next generation POWER processor/system performance across cache memory subsystem interconnects etc. You will be part of highly experienced and talented team of engineers doing processor/system performance modeling hardware bringup Pre-silicon verification & post-silicon validation and microarchitecture development and will work closely with Processor/System design architects.
“AAs a Hardware Performance Analyst your responsibilities would be to work on multiple HW performance projects

• Develop test and validation plan for hardware bringup pre-silicon performance verification and post-silicon performance validation
• Develop kernels and methodologies to correlate software model with hardware performance.
• Interact and collaborate with hardware software and firmware development teams during system bringup and ensure the system meets its performance objectives
• Root causing of fails in simulation for performance changes/difference between Hardware and simulator
• Build automation frameworks test cases and result analysis scripts.
• Design and develop model to simulate sub-systems like cache interconnect and memory protocols
• Working with Architects/Research teams for optimizing architecture and system design improving performance of next generation POWER processor and system.
• Demonstrate leadership in characterizing benchmarks workloads and use cases (application code) and proposing system design optimisations to improve system level performance.
• Independently own system unit and successfully drive performance missions.”

Required Technical and Professional Expertise

• “Must have lead multiple HW projects
• Programming: C++ SystemC Scripting (Python Perl) Assembly
• Experience developing hardware models for the server sub-systems like cache interconnect and memory units
• Experience doing Performance Analysis Workload Characterization & Performance Optimization
• Experience in performing hardware performance validation and correlation
• Experience in server class system bringup and optimization
• Good understanding of Processor microarchitecture System architecture Memory & IO subsystem architecture
• Demonstrate leadership in characterizing benchmarks workloads and use cases and proposing microarchitectural optimizations
• Understanding architecture and micro-architecture features of POWER processor core and system.
• Good communication & presentation skills and to work with geographically distributed collaborators
• Ability to learn new areas quickly”

Preferred Technical and Professional Expertise

• “Knowledge of Compilers
• Knowledge of Assembley Programming”