Testchip Backend Lead

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
• 8 years of experience with Tapeout of SoC or test chips in the latest process technologies.
• Experience with Low-Power Double Data Rate (LPDDR) and Serializer/Deserialize (SERDES ) IP integration such as Peripheral Component Interconnect Express (PCIe), Device-to-Device (D2D) Universal Chiplet Interconnect Express (UCIe), low power IP into SoC.

Preferred qualifications:

• Experience of multiple SoC Tapeouts.
• Experience with multiple foundries process design kits (PDKs).
• Experience with Testchip/SoC with cutting edge process technology.
• Experience in sign-off design, with expertise of physical design verification.

Experience in digital design fundamentals and methodologies, with the knowledge of physical design from definition to implementation and final tapeout.

Excellent statistics, data analysis, teamwork and communication skills.

About the job

Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

In this role, you will be part of Google's Silicon team, developing high performance and low power hardware to enable Google's continuous innovations in mobile devices. You will have an understanding of the latest technologies like Chiplet, Mobile-specific IPs and SoCs, with standard flip chip design. You will be responsible for driving the overall back-end of the test-chip in a tight schedule and working with Foundry, CAD, IP Team, and Process Technology team to ensure all the requirements are met.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Develop bump, micro-bump, chiplets plan to support new test-chip development.
• Work with packaging and architecture teams on chiplet and package interconnect design implementation.
• Develop an overall physical integration plan of new technologies such as D2D, chiplet interface, IO IPs.
• Drive all physical design milestones, quality, deliverables and work with front-end and IP teams to balance multiple engaging priorities and deliver tapeout with high quality and timely delivery.
• Execute and resolve issues of top-level and block-level for successful integration and tapeout.